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MICRF507 470mhz to 510mhz low-power fsk transceiver with +10d bm power amplifier radiowire is a registered trademark of micrel, inc. mlf is a registered trademark of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micre l.com march 2010 m9999-032210-b general description the MICRF507 is a fully integrated fsk transceiver with +10dbm power amplifier and transmit/receive switch. the device is targeted at automated meter reading (amr) applications in the china short range device (srd) frequency band of 470mhz to 510mhz. the device supports data rates up to 20kbps with pll divider modulation and up to 200kbps with vco modulation. the receiver achieves a sensitivity of -113dbm at a data rate of 2.4kbps while only consuming 12ma of supply current. the integrated power amplifier (pa) delivers +10dbm of output power while only consuming 21.5ma of supply current. power down supply current is a low 0.2a while retaining register information and a low 280a in standby mode where only the crystal oscillator is enabled. the receiver of the MICRF507 utilizes a zero if (zif) i/q architecture, integrating a low-noise amplifier (lna) with bypass mode, i/q quadrature mixers, three-pole sallen- key if channel pre-filters, and six-pole elliptic switched capacitor if filters, providing excellent selectivity, adjacent channel rejection and blocking performance. fsk demodulation is implemented digitally and a synchronizer, when enabled, recovers the received bit clock. a receive signal strength indicator (rssi) circuit indicates the received signal level over a 50db range. an integrated frequency error estimator (fee) and crystal tuning capability allow fine tuni ng of the rf frequency. the transmitter of the MICRF507 consists of an fsk modulator and power amplifier with output power adjustable from +10dbm to -3.5dbm in seven steps. modulation can be achieved by applying two sets of pll divider ratios or through direct vco modulation by varying vco tank capacitance. the MICRF507 requires a 2.0v to 2.5v supply voltage, operates over the -40 ? c to +85 ? c temperature range, and is available in a 32-pin mlf ? package. radiowire ? features ? -113dbm sensitivity at 2.4kbps encoded bit rate ? +10dbm power amplifier with seven gain steps ? 12ma receive supply current ? 21.5ma transmit supply current at +10dbm ? 0.2 a power down current (registers retain settings) ? 280a standby current (crystal oscillator enabled) ? data rates up to 20kbps with pll divider modulation ? data rates up to 200kbps with vco modulation ? integrated transmit and receive (t/r) switch ? lna with bypass mode ? zero if i/q receiver architecture ? if pre-amplifiers wi th dc-offset removal ? three-pole sallen-key if channel low-pass pre-filter ? six-pole elliptic switched c apacitor if lo w-pass filter ? 50khz to 350khz programmable baseband bandwidth ? 59db blocking at 1mhz offset ? 53db adjacent channel rejection at 500khz offset ? fsk digital demodulator with clock recovery ? 50db received signal strength indicator (rssi) ? frequency error estimator (fee) ? reference crystal tuning capability ? 2.0 to 2.5v supply voltage range ? -40 ? c to +85 ? c operating temperature range ? available in 32-pin mlf ? package (5.0mm x 5.0mm x 0.85mm) applications ? china short range device (srd) communications ? automated meter reading (amr) ? advanced metering infrastructure (ami) ? wireless remote meter reading
micrel, inc. MICRF507 march 2010 2 m9999-032210-b radiowire ? fsk transceiver selection guide............................................................................................... ................. 4 ordering info rmation ........................................................................................................... .............................................. 4 block di agram .................................................................................................................. .................................................. 4 pin confi guration .............................................................................................................. ................................................. 5 pin descr iption ................................................................................................................ ................................................... 5 absolute maximum ratings (1) ............................................................................................................................... ............ 7 operating ratings (2) ............................................................................................................................... ............................ 7 electrical characteristics (4) ............................................................................................................................... ................ 7 functional d escripti on ......................................................................................................... ........................................... 10 control (3-wire) interface ..................................................................................................... ................................. 10 reading ........................................................................................................................ ......................................... 13 control interf ace ti ming....................................................................................................... ................................. 14 power-on reset ................................................................................................................. ................................... 14 clock gene ration ............................................................................................................... .............................................. 15 crystal oscilla tor (x co) ....................................................................................................... ........................................... 16 bitsync_clk (receiver bi t synchroniza tion clock)............................................................................... ........... 17 bitrate_clk (transmitte r bit rate clock) ....................................................................................... ................. 17 modulator_clk (vco modulator clock)............................................................................................ ............ 17 data interface and bit synchr onization ......................................................................................... ................................ 17 sync_en = 0 .................................................................................................................... ...................................... 19 sync_en = 1 .................................................................................................................... ...................................... 19 additional considerations in the use of synchronize r (sync_ en = 1) ............................................................. ..... 19 frequency sy nthesizer.......................................................................................................... .......................................... 20 vco............................................................................................................................ ........................................... 22 charge pump .................................................................................................................... .................................... 22 pll f ilter ..................................................................................................................... .......................................... 22 lock detect .................................................................................................................... ....................................... 23 receiver ....................................................................................................................... ..................................................... 24 front end...................................................................................................................... ......................................... 24 sallen-key filters ............................................................................................................. ..................................... 25 switched capac itor filter ...................................................................................................... ................................ 25 rssi ........................................................................................................................... ........................................... 25 fee ............................................................................................................................ ........................................... 26 xcotune proce dure example ...................................................................................................... ................................... 27 transmit ter.................................................................................................................... .................................................... 28 power amp lifier ................................................................................................................ ..................................... 28 frequency m odulation........................................................................................................... ................................ 29 divider m odulatio n ............................................................................................................. ................................... 30 vco modulation and the modulator............................................................................................... ....................... 30 modulator filter ............................................................................................................... ...................................... 32 system modes and initialization................................................................................................ ..................................... 33 start-up and in itialization.................................................................................................... ................................... 33 modes of op eration............................................................................................................. .................................. 33 mode tran siti ons............................................................................................................... .................................... 33 message coding and forma tting .................................................................................................. ................................. 34 dc balanced line co ding........................................................................................................ ............................. 34 message formatti ng: preamble................................................................................................... ......................... 34
micrel, inc. MICRF507 march 2010 3 m9999-032210-b typical app lication ............................................................................................................ .............................................. 35 bill of ma terials.............................................................................................................. ................................................... 36 layout cons iderations .......................................................................................................... .......................................... 37 layer defi nition ............................................................................................................... ...................................... 37 grounding...................................................................................................................... ........................................ 37 rf traces...................................................................................................................... ........................................ 37 supply r outing................................................................................................................. ..................................... 37 pll loop f ilter................................................................................................................ ...................................... 37 overview of pr ogramming bits................................................................................................... .................................... 38 detailed description of progra mming bits....................................................................................... ............................. 39 package info rmation............................................................................................................ ............................................ 46
micrel, inc. MICRF507 march 2010 4 m9999-032210-b radiowire ? fsk transceiver selection guide device frequency range maximum data rate receive current supply voltag e transmit cu rrent package micrf505 850mhz to 950mhz 200kbps 13.5ma 2.0 to 2.5v 28ma mlf-32 micrf505l 850mhz to 950mhz 200kbps 13.5ma 2.25 to 5.5v 28ma mlf-32 micrf506 410mhz to 450mhz 200kbps 12ma 2.0 to 2.5v 21.5ma mlf-32 MICRF507 470mhz to 510mhz 200kbps 12ma 2.0 to 2.5v 21.5ma mlf-32 ordering information part number j unction temperature range package MICRF507yml tr -40 to +85c pb-free 32-pin mlf ? block diagram
micrel, inc. MICRF507 march 2010 5 m9999-032210-b pin configuration 32-pin mlf ? pin description pin number pin name type pin func tion 1 rfgnd lna and pa ground. 2 ptatbias o connection for bias resistor. 3 rfvdd lna and pa power supply. 4 rfgnd lna and pa ground. 5 ant i/o antenna input/output. 6 rfgnd lna and pa ground. 7 rfgnd lna and pa ground. 8, 16, 17, 32 nc no connect. leave these pins floating. 9 cibias o connection for bias resistor. 10 ifvdd if/mixer power supply. 11 ifgnd if/mixer ground. 12 ichout o test pin. 13 qchout o test pin. 14 rssi o received signal strength indicator. 15 ld o pll lock indicator. 18 dataclk o rx/tx data clock output. 19 dataixo i/o rx/tx data input/output. 20 io i/o 3-wire interf ace data in /output 21 sclk i 3-wire interface serial clock. 22 cs i 3-wire interface chip select. 23 xtalin i crystal oscillator input. 24 xtalout i/o crystal oscillator output or external reference input. 25 digvdd digital power supply.
micrel, inc. MICRF507 march 2010 6 m9999-032210-b pin description (continued) pin number pin name type pin function 26 diggnd digital ground. 27 cpout o pll charge pump output. 28 gnd substrate ground. 29 varin i vco varactor tune voltage input. 30 vcognd vco ground. 31 vcovdd vco power supply. exposed paddle ground.
micrel, inc. MICRF507 march 2010 7 m9999-032210-b absolute maximum ratings (1) supply voltage (v dd )...................................................+2.7v voltage on any pin (gnd = 0v). ............. -0.3v to +2.7v lead temperature (solde ring, 4sec .) ......................... 300c storage temperature (t s ) ..........................-55c to +150c esd rating (3) .................................................................. 2kv operating ratings (2) supply voltage (v in ) .................................. +2.0v to +2.5v rf frequencies ................................ 470mhz to 510mhz encoded bit ra te ................................................ 200kbps ambient temperature (t a ) .......................?40c to +85c package thermal resistance 32-pin mlf ? ( ja ) ........................................41.7c/w electrical characteristics (4) f rf = 490mhz, f xtal = 16mhz, MICRF507 development board, modulation type = closed-loop vco modulation, sync_en bit = 1, v dd = 2.5v; t a = 25c, the term ?bit rate? refers to encoded bit rate throughout the ec table (see figure 24), bold values indicate ?40c< t a < +85c, unless noted. symbol parameter condition min typ max units f rf rf frequency operating range 470 510 mhz v dd power supply 2.5 v power down current 0.2 3 a standby current 280 a vco and pll section reference frequency 4 40 mhz 490mhz to 490.5mhz 0.7 ms pll lock time, 3khz bandwidth 485mhz to 495mhz 1.3 ms pll lock time, 20khz bandwidth 490mhz to 490.5mhz 0.3 ms rx ? tx 1.0 tx ? rx 1.0 standby to rx 1.0 switch time, 3khz loop bandwidth standby to tx 1.0 ms crystal oscillator start-up time with MICRF507 development board bom 1.0 ms v cpout = 1.1v, cp_hi = 0 100 125 170 a charge pump current v cpout = 1.1v, cp_hi = 1 420 500 680 a transmit section r load = 50 , pa[2:0] = 111 10 dbm p out output power r load = 50 , pa[2:0] = 001 -3.5 dbm over temperature range 1 db output power variation relative to v dd = 2.5v, t a = 25c v dd = 2.0v -2 db r load = 50 , pa[2:0] = 111 21.5 ma r load = 50 , pa[2:0] = 001 10.5 ma transmit mode current consumption r load = 50 , pa[2:0] = 000 8.0 ma single-sided frequency deviation (5) 10 250 khz vco modulation 200 kbps maximum bit rate divider modulation 20 kbps
micrel, inc. MICRF507 march 2010 8 m9999-032210-b electrical characteristics (4) (continued) symbol parameter condition min typ max units 38.4kbps, = 2, 20dbc 140 khz 125kbps, = 2, 20dbc 550 khz occupied bandwidth (5) 200kbps, = 2, 20dbc 800 khz 2 nd harmonic (5) -43 -36 dbm 3 rd harmonic (5) -59 -36 dbm spurious emission in restricted bands < 1ghz (5) -54 dbm spurious emission < 1ghz (5) -36 dbm spurious emission > 1ghz (5) -30 dbm receive section all functions on 12 lna bypassed 10.3 switch cap filter bypassed, lna on 9.8 rx current consumption both switch cap filter and lna bypassed 8 ma rx current consumption variat ion over temperature 2 ma 2.4kbps, = 16 -113 4.8kbps, = 16 -111 19.2kbps, = 4 -107 38.4kbps, = 4 -104 76.8kbps, = 2 -101 125kbps, = 2 -100 receiver sensitivity (ber 10 -3 ) 200kbps, = 2 -97 dbm 125kbps, 125khz deviation, lna on +7 125kbps, 125khz deviation, lna bypassed +12 receiver maximum input power 20kbps, 40khz deviation +2 dbm over temperature 2 db receiver sensitivity tolerance over power supply range 1 db receiver baseband bandwidth 50 350 khz co-channel rejection, ber = 10 -3 19.2kbps, = 6, pf_fc[1:0] = 01, f cut = 133khz -8 db 500khz spacing 53 db adjacent channel rejection, both interferer and desired signal are modulated at 19.2 kbps encoded bit rate, = 6, pf_fc[1:0] = 01, f cut = 133khz, ber = 10 -3 1mhz spacing 58 db 1mhz 59 db 2mhz 60 db 5mhz 47 db cw blocking above desired signal, desired signal is modulated at 19.2kbps, = 6, 3db above sensitivity, pf_f c[1:0] = 01, f cut = 133khz, ber = 10 -3 10mhz 60 db
micrel, inc. MICRF507 march 2010 9 m9999-032210-b electrical characteristics (4) (continued) symbol parameter condition min typ max units p 1db 1db compression -34 dbm input ip3 2 tones with 1mhz separation -25 dbm lo leakage -90 dbm <1ghz -57 dbm spurious emission (5) >1ghz -47 dbm input impedance with no matching components 33+7j ? rssi dynamic range 50 db p in = -110dbm 0.9 v rssi output range p in = -60dbm 2 v digital inputs/outputs v ih logic input high 0.7*v dd v dd v v il logic input low 0 0.3*v dd v clock/data frequency (5) 10 mhz clock/data duty cycle (5) 45 55 % notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handli ng precautions recommended. human body mo del; 1.5k in series with 100pf. 4. specification for packaged product only. 5. guaranteed by design.
micrel, inc. MICRF507 march 2010 10 m9999-032210-b functional description control (3-wire) interface general the MICRF507 operation is controlled through a set of 8- bit registers. the chip has a total of 23 readable registers (addresses 0-22) of which 22 (addresses 0-21) are writeable. through this regi ster set, the user can set the MICRF507 in transmit or receive mode, program the carrier frequency, and select a bit rate, among other options. table 1 identifies all register bits. table 26 gives more detail and table 27 shows the register fields grouped by category, with don?t-care and mandatory bits omitted. some bits shown as ?0? or ?1? are mandatory bits and must always be written with the val ues given. other bits marked as ?-? are ?don?t care? bits. registers are accessed seri ally through the control interface consisting of the cs, io, and sclk pins. positive-going pulses at sclk serve to clock bits in and out of io at a rate determined by the user. when io is an input, falling edges of sclk strobe each bit in; when io is an output, each bit appears at io after the rising edge of sclk. the io is an input for entry of starting addresses, the r/w bit, and bytes being written to registers, and an output for bytes read from registers. cs enables transactions at t he control interface, active high. transitions at the other two pins are ignored when cs is low. this allows the MICRF507 to share sclk and io with other devices as long as they have separate cs lines. to start a transaction (with sclk and cs initially low), bring cs high. to end a transaction (with sclk low), bring cs low. to write a bit into io (when io is an input); first bring sclk high and drive io with the bit level to be input (in either order, or simultaneously). then bring sclk low. to read a bit out of io (when io is an output); first bring sclk high and read the level on io. then bring sclk low (in either order, or simultaneously). the first byte to be clocked in during a transaction is made of seven bits (msb first) of register address followed by the r/w bit, 0 for write, 1 fo r read. then, one or more bytes to be written to or read from registers are clocked in or out respectively, always msb first.
micrel, inc. MICRF507 march 2010 11 m9999-032210-b adr data field a6?a0 d7 d6 d5 d4 d3 d2 d1 d0 0000000 lna_by pa2 pa1 pa0 sync_en mode1 mode0 ?1? 0000001 modulation1 modulation0 ?0? ?0 ? rssi_en ld_en pf_fc1 pf_fc0 0000010 cp_hi sc_by ?0? pa_by outs3 outs2 outs1 outs0 0000011 ?1? ?1? ?0? vco_ib2 vco_ib1 vco_ib0 vco_freq1 vco_freq0 0000100 mod_f2 mod_f1 mod_f0 mod_i 4 mod_i3 mod_i2 mod_i1 mod_i0 0000101 - - ?0? ?1? mod_a3 mod_a2 mod_a1 mod_a0 0000110 - mod_clks2 mod_clks1 mod_clks0 bitsync_cl ks2 bitsync_clks1 bitsync_clks0 bitrate_clks2 0000111 bitrate_clks1 bitrate_clks0 refclk_k5 refc lk_k4 refclk_k3 refclk_k2 refclk_k1 refclk_k0 0001000 ?1? ?1? ?0? scclk4 scclk3 scclk2 scclk1 scclk0 0001001 ?0? ?0? ?1? xcotune4 xcotune3 xcotune2 xcotune1 xcotune0 0001010 - - a0_5 a0_4 a0_3 a0_2 a0_1 a0_0 0001011 - - - - n0_11 n0_10 n0_9 n0_8 0001100 n0_7 n0_6 n0_5 n0_4 n0_3 n0_2 n0_1 n0_0 0001101 - - - - m0_11 m0_10 m0_9 m0_8 0001110 m0_7 m0_6 m0_5 m0_4 m0_3 m0_2 m0_1 m0_0 0001111 - - a1_5 a1_4 a1_3 a1_2 a1_1 a1_0 0010000 - - - - n1_11 n1_10 n1_9 n1_8 0010001 n1_7 n1_6 n1_5 n1_4 n1_3 n1_2 n1_1 n1_0 0010010 - - - - m1_11 m1_10 m1_9 m1_8 0010011 m1_7 m1_6 m1_5 m1_4 m1_3 m1_2 m1_1 m1_0 0010100 ?1? ?0? ?1? ?0? ?0? ?0? ?1? ?1? 0010101 - - - - feec_3 feec_2 feec_1 feec_0 0010110 fee_7 fee_6 fee_5 fee_4 fee_3 fee_2 fee_1 fee_0 names of programming bits. unused bits (?-?) and mandatory bits (?1? or ?0?) are shown. changes to mandatory bits may cause malfunction. table 1. control registers
micrel, inc. MICRF507 march 2010 12 m9999-032210-b writing this method is used to write either to one register (see figure 1), or any number of registers with consecutive addresses up to all 22 writeable registers (see figure 2) in a single transaction. procedure: ? bring cs active (high). io is initially an input (and remains so for the duration of the transaction). ? clock in a byte consisting of the address bits and the r/w bit. the first seven bits are the address (starting with msb) of the register, or the first register if more than one, to be written. the eighth bit is the r/w bit, which is 0 as this is a write operation. ? clock in one or more bytes, msb of each byte first. ? bring cs low to end the transaction. bits passing through io are clocked serially into pre- buffers, then transferred in parallel to the actual registers upon de-assertion of cs. figure 1. writing a byte into a register figure 2. writing bytes into n+1 registers at consecutive addresses starting with address i
micrel, inc. MICRF507 march 2010 13 m9999-032210-b reading any number of registers with consecutive addresses, from one up to all 23, can be read. procedure: ? bring cs active (high). io is initially an input. ? clock in a byte consisting of the address bits and the r/w bit. the first seven bits are the address (starting with msb) of the register, or the first register if more than one, to be read. the eighth bit is the r/w bit, which is 1 as this is a read operation. after the r/w bit is clocked in (falling edge of sclk), the next rising edge on sclk will enable io as an output for the duration of the transaction. ? clock out 8 bits per register (one or more) to be read through io, msb first. rising edges of sclk bring each bit to io. the user can then conveniently sample the bit at the next falling edge of sclk. ? bring cs low to end the transaction. io reverts to being an input. figure 3 shows how to read one register. to read more registers at consec utive addresses, continue pulsing sclk eight times for each register to be read before de-asserting cs. figure 3. reading a byte from a register figure 4. definitions of control interface timing parameters
micrel, inc. MICRF507 march 2010 14 m9999-032210-b control interface timing figure 4 and table 2 give the timing specifications for the control interface. when in receive or transmit mode (but not power-down or standby mode), an additional timing constraint applies: elapsed time between falling edges of cs must be a minimum of 2/f c , where f c is the synthesizer?s comparison frequency (also called phase detector frequency). f c = f xco /m, xco xco c f 2m time min m f f = = where m = m0 when receiving or transmitting with vco modulation, and m = max{m0, m1} when transmitting with divider modulation. values symbol parameter min. typ. max. units t high min. high time of sclk 20 ns t low min. low time of sclk 20 ns t fall fall time of sclk 1 s t rise rise time of sclk 1 s t csr time from rising edge of cs to falling edge of sclk 50 ns t csf min. delay from rising edge of cs to rising edge of sclk 25 ns t write min. delay from valid io to falling edge of sclk during a write operation 20 ns t read min. delay from rising edge of sclk to valid io during a read operation (assuming load capacitance of io is 25pf) 75 ns t por power on reset time 4.6 9 ms table 1. control interface timing power-on reset the power-on reset time (t por ), given in table 2, is defined as the time from application of supply voltage to completion of power on reset. to determine when the chip has completed its power-on without waiting for the worst-case time (maximum t por ) , do the following: ? write hex 03 (binary 00000011) to register 0. this puts the chip in standby mode. ? read register 0. if the value read is binary 00000011, then exit; power-on is complete. if not, go to previous step and repeat. because registers are initially in an unknown state after power-on (exception: mode[1:0] initializes to 00), always enter a complete set of register values as the first transaction, and always enter only nonzero values for n and m. figure 5. power-on programming flowchart
micrel, inc. MICRF507 march 2010 15 m9999-032210-b clock generation the MICRF507?s crystal oscillator: ? serves as the reference fo r the synthesizer that is the carrier and loca l oscillator source. ? is divided down to clock the switched-capacitor if filter. ? is divided down to generate three other clocks: bit rate clock, bit synchronization clock, and modulator clock figure 6 shows the oscillator with its frequency-shifting capacitor bank (controlled by the register field xcotune) and the frequency dividers that derive the latter three clocks from its output. this division occurs in two stages. first, the xco output is divided by the 6-bit field refclk_k, which has allowable values between 1 and 63. then, for each of the three clocks, another field (bitsync_clks, bitrate_clks, and modclks, respectively) selects the number of further divisions by 2. complete relationships of field values and resultant frequencies are given below for each clock. field name number of bits location of bits description xcotune 5 reg9[4:0] crysta l oscillator trimming. refclk_k 6 reg7[5:0] reference clock divider. bitrate_clks 3 reg6[0], reg7[7:6] transmitter bit rate clock setting. see figure 9 and ?data interface and bit synchronization? section for more details. mod_clks 3 reg6[6:4] vco modulator clock setting, set the modulator clock to either 8x or 16x the bit rate clock. bitsync_clks 3 reg6[3:1] receiver bit synchronization clock setting, always set bit synchronization clock to 16x the bit rate clock. see figure 9 and ?data interface and bit synchronization? section for more details. table 3. register bit fields for clock generation figure 6. MICRF507 clock sources
micrel, inc. MICRF507 march 2010 16 m9999-032210-b crystal oscillator (xco) the crystal oscillator?s role as the synthesizer reference demands very good phase and frequency stability. as shown in figure 7, the external components required for the oscillator are a crystal, connected bet ween pins 23 and 24, and loading capacitors. pin 24 xtalout pin 23 xtalin c9 1.5pf c8 1.5pf y1 tn4-26011 figure 7. crystal oscillator circuit the load capacitance c l seen between the crystal terminals is: pin xcotune 9 8 l c c c 1 c 1 1 c + + + = where c xcotune is the capacitance of the internal adjustable capacitor bank, and c pin is defined as the internal chip capacitance when xcotune bits are all zeros, plus pcb stray capacitance across pins 23 and 24. the value of c pin is about 6pf. the loading capacitor values required depend on the total c l specified for the crystal for oscillation at the desired frequency. it is possible to tune the cr ystal oscillator internally by giving the 5-bit register field xcotune a non-zero value, which causes internal capacitors to be switched across the crystal. as this capacitance increases, frequency decreases. when xcotune is set to its maximum value of 31, approximately 4.5pf additional capacitance is connected across the crystal pins. the xco tuning can be used to cancel crystal resonant frequency error, both initial and with temperature. it can be used in combination with the frequency error estimator (fee). see ?fee? section. the crystal used is a tn4-26011 from toyocom. specification: ? package tsx-10a, ? nominal frequency 16.000000mhz ? frequency tolerance 10ppm ? frequency stability 9ppm, load capacitance 9pf ? pulling sensitivity 15ppm/pf to achieve 9pf load capacitance required to center tn4-26011 at 16mhz, set the external capacitors to 1.5pf and xcotune=16 dec . figure 8 shows the tuning range for two different capacitor values, 1.5pf and zero (external capacitors omitted). external capacitor values will strongly affect the tuning range. using 1.5pf with the above crystal gives a tuning range that is approximately symmetrical about the center frequency. -60,0 -40,0 -20,0 0,0 20,0 40,0 60,0 80,0 100,0 0 8 16 24 32 xco bitvalue [ppm] 2x1.5pf 2x0pf figure 8. xco tuning with the xcotune field the start-up time of the cyst al oscillator, given in table 4, is about a millisecond and increases with capacitance. when the MICRF507?s main mode is switched from power down mode to transmit mode via standby mode, or to receive mode via standby mode, only the xco is energized at first. current consumption during this prestart period is approximately 280 a (the same as for standby mode). after the xco amplitude is sufficient to trigger the m-counter and produce two pulses at its output, the remaining circuits on the chip are powered on. xcotune start-up time (s) 0 590 1 590 2 700 4 700 8 810 16 1140 31 2050 table 4. typical crystal oscillator start-up time with c8 = c9 = 1.5pf
micrel, inc. MICRF507 march 2010 17 m9999-032210-b an external reference clock, when used instead of a crystal, should be applied to pin 24 (xtalout) with pin 23 (xtalin) not connected. to maintain proper dc biasing within the chip, use ac-coupling between the external reference and the xtalout-pin. bitsync_clk (receiver bit synchronization clock) the frequency of the bit synchronization clock f bitsync_clk , is a function of the crystal oscillator frequency f xco and the values of the register fields refclk_k and bitsync_clks: ) - (7 xco k bitsync_cl 2 refclk_k f f ks bitsync_cl = the bit synchronizer uses a clock that needs to be programmed to 16 times the actual bit rate. as an example, a bit rate of 20kbps needs a bit synchronizer clock with frequency of 320khz. refer to figure 9 and ?data interface and bit synchronization? section for more details. bitrate_clk (transmitter bit rate clock) the frequency f bitrate_clk of bitrate_clk is a function of the crystal oscillator frequency f xco and the values of the register fields refclk_k and bitrate_clks: ks) bitrate_cl - (7 xco k bitrate_cl 2 refclk_k f f = in transmit mode, when sync_en = 1, bitrate_clk appears on the dataclk pin. its frequency is equal to the bit rate. example; a bit rate of 20 kbit/sec requires an f bitrate_clk of 20khz. refer to figure 9 and the ?data interface and bit synchronization? subsection for more details. modulator_clk (vco modulator clock) the frequency f mod_clk of modulator_clk is a function of the crystal oscillator frequency f xco and the values of the register fields refclk_k and mod_clks: ) - (7 xco mod_clk 2 refclk_k f f mod_clks = the modulator clock is used if vco modulation method is selected. set the modulator clock frequency to either 8x or 16x the bit rate. see ?vco modulation and the modulator? subsection for more information. bitrate_clks[2:0] bitsync_clks[2:0] mod_clks[2:0] corresponding clock frequency (f xco is crystal frequency) 000 f xco /(128xrefclk_k) 001 f xco /(64xrefclk_k) 010 f xco /(32xrefclk_k) 011 f xco /(16xrefclk_k) 100 f xco /(8xrefclk_k) 101 f xco /(4xrefclk_k) 110 f xco /(2xrefclk_k) (*) 111 f xco /refclk_k (*) (*) can not be used as bitrate_clk. table 5. generation of bitrate_clk, bitsync_clk and mod_clk data interface and bit synchronization transmitted and received data bits are coupled to the MICRF507 serially through the data interface. this data interface consists of the dataixo and dataclk pins. this is a separate interface from the control interface (cs, io, and sclk), for which see control (3-wire) interface. figure 9 shows the data interface circuitry aboard the MICRF507. dataixo is an input during transmission, whereas during reception a driver is enabled and it becomes an output. dataclk is always an output. a rule that applies when using vco modulation is: after commanding the MICRF507 to enter transmit mode, the microcontroller shall tri-stat e the driver connected to dataixo to leave that pin floating until the microcontroller begins sending data. see ?mode transitions? section for more details. the data interface can be programmed for synchronous and non-synchronous operation according to the setting of the sync_en bit; see table 7.
micrel, inc. MICRF507 march 2010 18 m9999-032210-b field name number of bits location of bits description reference sync_en 1 reg0[3] synchronizer mode bit table 7 table 6. register bit fields for data interface and bit synchronization sync_en state comments 0 rx: bit synchronization off transparent reception of data 0 tx: dataclk pin off transparent transmission of data 1 rx: bit synchronization on bit clock is generated by transceiver 1 tx: dataclk pin on bit clock is generated by transceiver table 7. synchronizer mode bit figure 9. data interface and synchronization d q bit sync bitrate_clk from demod recovered clock receive mode enable d q sync_en sync_en = 0 sync_en = 1 sync_en = 0 sync_en = 1 transmit receive 19 18 dataixo dataclk to transmitter filter & data slicer bitsync_clk transmit data path receive data path
micrel, inc. MICRF507 march 2010 19 m9999-032210-b dataclk dataixo mode sync_en direction signal direction signal/function 0 output 0 input modulates carrier directly (asynchronously) transmit 1 output bitrate clock input sampled at rising edge of bitrate clock; latched output modulates carrier 0 output 0 output raw output from demodulator receive 1 output clock recovered by bit synchronizer output filtered and latched demodulator output; transitions occur at rising edge of dataclk table 8. synchronizer mode and data interface in sync mode (sync_en bit set to 1), the transmitted bit stream is clocked with the precision of the MICRF507?s crystal oscillator, which relaxes timing accuracy requirements on the data source. during reception, the synchronizer ensures that tr ansitions of dataixo occur only at rising edges of dataclk, without edge jitter or internal glitches. receiver s ensitivity values given in the electrical characteristics t able are measured with sync_en = 1; with sync_en = 0, as mu ch as 3-6 db of sensitivity could be lost. sync_en = 0 when sync_en = 0, the i nput signal at dataixo modulates the transmitter directly during transmission and the output signal from dataixo is the raw demodulator output. dataclk remains fixed at a logic low level during both transmission and reception. sync_en = 1 during transmission when sync_en = 1 the data bit stream entering dataixo is buffered with a flip-flop strobed at the rising edge of bitrate_clk, and the output of the flip- flop modulates the transmitter. bitrate_clk is brought out at the dataclk output. figure 10 shows the relationship of dataclk a nd dataixo transitions. dataixo dataclk figure 10. data interface in transmit mode during reception, the bit sy nchronizer recovers the received signal?s clock. this recovered clock strobes a flip- flop that samples in mid-bit-period the demodulated and filtered bit stream. the dataclk output brings out the recovered clock. dataixo ( an output during reception) brings out the synchronized data stream, which has its transitions at rising edges of dataclk. see figure 11. dataixo dataclk figure 11. data interface in receive mode by being in control of bit timing, the MICRF507 is effectively the ?master.? for maximum timing margin, the microcontroller, as the ?slave,? can present or sample (during transmit and receive, respectively) each new bit at the dataixo pin at falling edges of dataclk. additional considerations in the use of synchronizer (sync_en = 1) two clock signals, bitrate_clk and bitsync_clk, must be properly programmed when using the synchronizer. bitrate_clk, used in transmission, must be set to a frequency equal to the bit rate. bitsync_clk, used in recept ion, must have a frequency 16 times the bit rate. these frequencies are controlled by the crystal oscillator frequency and the se ttings of register fields, as described in the ?clock generation? section. bit clocking of the incoming signal must agree with the receiver?s local clocking within 2.5% (easily met with 100 ppm or better crystals). for example, if f bitsync_clk is 16x19.231kbps, the incoming bit rate can be between 0.975x19.231kbps to 1.025x19.231kbps. all incoming messages must start with a 0101? preamble so that the synchronizer can acquire the incoming clock. a 24-bit preamble is typically used; a minimum of 22 bits is required.
micrel, inc. MICRF507 march 2010 20 m9999-032210-b frequency synthesizer the MICRF507 frequency synthesizer is an integer-n phase-locked loop consisting of: ? a reference source, made of an m-divider clocked by the crystal oscillator ? a voltage controlled oscillator (vco) ? a programmable frequency divider made of an n-divider, an a-divider, and a dual modulus prescaler ? a phase/frequency detector the loop filter is external for flexibility and can be a simple passive circuit. the phase/frequency detector compares the reference frequency (from the m-divider) with the vco output fed through the programmable frequency divider. the charge pump output of the phase/frequency detector, after filtering, controls the vco, closing the loop and forcing the error between the reference frequency and the divided vco frequency to zero. the block diagram, figure 12, shows the basic elements and arrangement of a pll-based frequency synthesizer. the MICRF507 has a dual modulus prescaler for increased frequency resolution. in a dual modulus prescaler the main divider is split into two parts, the main part n and an additional divider a, where a < n. both dividers are clocked from the output of the dual-modulus prescaler, but only the output of the n divider is fed into the phase detector. the prescaler will first divide by 16. both n and a count down until a reaches zero, at which point the prescaler is switched to a division ratio 16+1. at this point, the divider n has completed a counts. counting continues until n reaches zero, which is an additional n-a counts. at this point, the cycle repeats. field name number of bits location of bits description m0 12 reg13[3:0], reg14[7:0] m0 counter a0 6 reg10[5:0] a0 counter n0 12 reg11[3:0], reg12[7:0] n0 counter m1 12 reg18[3:0], reg19[7:0] m1 counter a1 6 reg15[5:0] a1 counter n1 12 reg16[3:0], reg17[7:0] n1 counter cp_hi 1 reg2[7] high charge pump current (1= 500 a, 0 = 125a) vco_freq 2 reg3[1:0] frequency setting of vco (see table 11) vco_ib 3 reg3[4:2] vco bias current setting (see table 11) ld_en 1 reg1[2] lock detect function on/off table 9. register bit fields for frequency synthesizer
micrel, inc. MICRF507 march 2010 21 m9999-032210-b phase detector prescaler n-divider m-divider div 2 loop filter charge pump a-divider pa div 2 vco xco downconverter figure 12. pll block diagram a6?a0 d7 d6 d5 d4 d3 d2 d1 d0 0001010 - - a0_5 a0_4 a0_3 a0_2 a0_1 a0_0 0001011 - - - - n0_11 n0_10 n0_9 n0_8 0001100 n0_7 n0_6 n0_5 n0_4 n0_3 n0_2 n0_1 n0_0 0001101 - - - - m0_11 m0_10 m0_9 m0_8 0001110 m0_7 m0_6 m0_5 m 0_4 m0_3 m0_2 m0_1 m0_0 0001111 - - a1_5 a1_4 a1_3 a1_2 a1_1 a1_0 0010000 - - - - n1_11 n1_10 n1_9 n1_8 0010001 n1_7 n1_6 n1_5 n1_4 n1_3 n1_2 n1_1 n1_0 0010010 - - - - m1_11 m1_10 m1_9 m1_8 0010011 m1_7 m1_6 m1_5 m 1_4 m1_3 m1_2 m1_1 m1_0 table 10. register bit fields for pll
micrel, inc. MICRF507 march 2010 22 m9999-032210-b n, m, and a are numbers of length 12, 12 and 6 bits, respectively the synthesizer?s output frequency can be calculated from the following equation: () () a n 16 f a n 16 f m f f rf vco xco pd + = + = = 2 2 m 0 1 a 16 2m a n 16 f f xco rf + = where f pd : phase detector comparison frequency f xco : crystal oscillator frequency f vco : voltage controlled oscillator frequency f rf : rf carrier frequency the MICRF507 has two sets of register fields controlling the synthesizer?s frequency multiplication ratio; a0/n0/m0 and a1/n1/m1. during transmission using divider modulation (see ?divider modulation? section), bit values of ?0? and ?1? respectively select the 0 and 1 register field set. during reception and during transmission using vco modulation, only the 0 set is used. vco the vco has no external components. the three-bit field vco_ib controls vco bias current to optimize phase noise. the two bit field vco_freq controls a capacitor bank which determines the vco frequency range. these five bits are set according to the rf frequency as follows: rf freq vco_ib2 vco_ib1 vco_ib0 vco_freq1 vco_freq0 470- 482mhz 1 0 1 0 1 482- 497mhz 1 0 0 1 0 497- 510mhz 0 1 1 1 1 table 11. vco bit setting the tuning range, the rf frequency versus vco tune voltage (varactor input, pin 29), depends on the vco frequency setting as shown in as shown in figure 13. when the tuning voltage is in the range from 0.9v to 1.4v, the vco gain (as seen by the pll) is at its maximum, approximately 64 to 70mhz/v. note that the rf frequency is half of the pll frequency. it is recommended that the vco tune voltage stays in this range. the input capacitance at the varactor pin must be taken into consideration when design ing the pll loop filter. this is most critical when designing a loop filter with high bandwidth, which gives relatively small component values. the input capacitance is approximately 6pf. rf frequency vs varactor input voltage 450 460 470 480 490 500 510 520 530 540 00.40.81.21.622.4 varin voltage (v) rf frequency (mhz) 11 10 01 figure 13. rf frequency vs. varactor voltage and vco_ freq bits (v dd = 2.5v) charge pump the charge pump current can be set to either 125a or 500a by cp_hi (?1? 500a). this will affect the loop gain and, consequently, filter component values. for applications using high phase detector frequency and high pll bandwidth, use 500a charge pump current. pll filter the design of the pll f ilter strongly affects the performance of the frequency synthesizer. key parameters in pll filter design are loop bandwidth, the modulation method (vco modulation or divider modulation) and the bit rate. filter design also affect the switching time (important when frequency hopping) and phase noise. divider modulation requires the pll to lock on a new carrier frequency for every new data bit. as a rule of thumb, the pll loop bandwidth should be at least twice as high as the bit rate. in such cases it is recommended to use a third order filter to suppress the phase detector frequency. for vco modulation, the pll loop bandwidth should be less than 1/10 of the bit rate. if the loop bandwidth is high relative to the bit rate, the pll will keep the vco at a fixed frequency, preventing it from being modulated. the recommended third-order loop filter (made with external components) is shown in figure 14. when r2=0 and c3 is omitted, this reduces to a second-order loop filter.
micrel, inc. MICRF507 march 2010 23 m9999-032210-b c3 c1 pin 27 c p_out pin 29 var in c2 r2 r1 figure 14. second and third order loop filter table 12 shows three different loop filter designs, the first two for vco modulation and the last one for modulation using the internal dividers. the component values are calculated with rf frequency = 490mhz, vco gain = 67mhz/v as seen by the pll, and desired phase margin = 56o. other settings are shown in the table. the varin pin capacitance (pin 29) of 6pf can be neglected for the two filters with lowest bandwidth (which have r2=0 and relatively large values of c1). for other loop bandwidth and phase detector values, use the loop filter calculation tool in rf testbench software available on micrel?s website. lock detect a lock detector can be enabled by setting ld_en = 1. when pin ld is high, it indicates that the pll is in lock. after a control word is loaded ld will (typically) go low, then high again when the synthesizer has locked. ld also goes low initially when the pa (power amplifier) is turning on. after the transceiver has been put into receive or transmit mode, or after the power amplifier has been turned on, a low-to-high transition at ld can serve as an indicator that the synthesize r frequency has stabilized. encoded bit rate (kbps) pll bw (khz) charge pump ( a) phase detector freq. (khz) c1 c2 r1 r2 c3 vco >8 0.8 125 100 10nf 100nf 6.2k ? 0 nc vco >32 3.2 125 100 680pf 6.8nf 22k ? 0 nc divider <6.5 13 500 500 390pf 8.2nf 5k ? 68k ? 18pf table 12. loop filter component values
micrel, inc. MICRF507 march 2010 24 m9999-032210-b receiver field name number of bits location of bits description reference by_lna 1 reg0[7] lna bypass on/off pf_fc 2 reg1[1:0] pre-filt er corner frequency table 14 sc_by 1 reg2[6] bypass of swit ched capacitor filter on/off scclk 5 reg8[4:0] switched cap clock divider rssi_en 1 reg1[3] rssi function on/off feec 4 reg21[3:0] fee control bits table 15 fee 8 reg22[7:0] fee value (read only) table 13. register bit fields for receiver the receiver is a zero intermediate frequency (zif) type employing low-power, fully in tegrated low-pass filters. a low noise amplifier (lna) drives a quadrature mixer pair. the mixer outputs feed two identical signal channels. each channel?s signal path has a pre-amplifier, a third order sallen-key rc low-pass pre-filter, a six-pole switched-capacitor filter (which determines actual selectivity), and finally a limiter. the limiter outputs then enter a demodulator which detects the relative phase of the baseband i and q signals. if the i channel signal lags the q channel, the fsk tone frequency lies above the lo frequency (data ?1?). if the i channel leads the q channel, then the fsk tone lies below the lo frequency (data ?0?). the output of the demodulator is available on the dataixo pin; in either raw form or latched with the recovered clock according to the setting of sync_en bit. an rssi (receive signal strength indicator) circuit indicates the received signal level. front end the MICRF507?s low-noise amplifier boosts the incoming signal prior to frequency conversion in order to prevent mixer noise from degrading overall front-end noise performance. the lna is a two-stage amplifier and has a nominal gain of approximately 23db at 490mhz. the front end has a gain of about 31db to34db. the gain varies by 1-1.5db over a 2.0v to 2.5v variation in power supply. the lna can be bypassed by setting bit lna_by to ?1?. this can be useful for very strong input signal levels. the front-end gain with the lna bypassed is about 12db. the mixers have about 10db of gain at 490mhz. with appropriate setting of the outs fi eld (register 2, bits d3 to d0), the differential outputs of the mixers can be made available at pins ichout and qchout. the output impedance of each mixer is about 8k ? . figure 15. lna input impedance resistance 32.4 ? 33.4 ? 34.4 ? reactance 7.9 ? 7.4 ? 6.4 ? mhz 470 490 510 marker 1 2 3
micrel, inc. MICRF507 march 2010 25 m9999-032210-b the front end?s input impedance, with no matching network, is close to 50 ? as shown in figure 15. this gives an input reflection coefficient of about -13db. although the receiver does not require a matching network to optimize the gain, a matching network is recommended for harmonic suppression during transmission and for improved selectivity in reception. sallen-key filters each if channel includes a pre-amplifier and a pre-filter. the preamplifier has a gain of 22db. the if amplifier also removes dc offset. gain varies by less than 0.5db over a 2.0v to 2.5v variation in power supply. the pre-filter is implemented as a three-pole sallen-key low-pass filter. it protects the sw itched-capacitor filter that follows it from strong adjacent channel signals and also serves as an anti-aliasing filter. it is programmable to four different cut-off frequencies as shown in table 14. pf_fc1 pf_fc0 cutoff (3db filter corner) 0 0 100khz 0 1 150khz 1 0 230khz 1 1 340khz table 14. pre-filter bit field switched capacitor filter the main if channel filter is a switched-capacitor implementation of a six-pole elliptic low pass filter. this meets selectivity and dynamic range requirements with minimum total capacitance. the cut-off frequency of the switched-capacitor filter is adjustable by changing the clock frequency. a 6-bit frequency divider, programmed by the scclk[5:0] field, is clocked by the crysta l oscillator. its output, which is 20 times the filter?s cutoff frequency, is then divided by 4 to generate the correct non-overlapping clock phases needed by the filter. the cut-off frequency of the filter is given by: scclk 40 f f xco cut ? = f cut : filter cutoff frequency f xco : crystal oscillator frequency scclk: switched capacitor filt er clock, bits scclk[4:0] (bit 0 has a mandatory value of ?0?). for instance, for a crystal frequency of 16mhz and if the 6 bit divider divides the input frequency by 4, the cut-off frequency of the sc filter is 16mhz/(40 x 4) = 100khz. a first-order rc low-pass filter removes clock frequency components from the signal at the switched-capacitor filter output. the pre-filter and switched-ca pacitor filters in cascade must pass the full if bandwidth of the received signal. in a zero-if receiver such as the MICRF507 this bandwidth is as follows: 2 r f f f b dev offset bw + + = where f bw : needed receiver bandwidth; f cut above should not be smaller than f bw [hz] f offset : total frequency offset between receiver and transmitter [hz] f dev : single-sided frequency deviation [hz] r b : the bit rate in bits/sec rssi rssi 33kohm, 1nf, 125kbps, bw=200khz, vdd=2.5v 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 -125 -115 -105 -95 -85 -75 -65 -55 -45 -35 -25 pin [dbm] rssi [v] figure 16. rssi voltage c10 1nf r2 33k pin 14 rssi rs si figure 17. rssi network figure 16 shows a typical plot of the rssi voltage as a function of input power. the rssi termination network is shown in figure 17. the rssi has a dynamic range of about 50db from about -110dbm to -60dbm input power. when an rf signal is received, the rssi output increases and can serve as a signal presence indicator. it could be used to wake up external circuitry that conserves battery life while in a sleep mode. note that rssi only functions in receive mode.
micrel, inc. MICRF507 march 2010 26 m9999-032210-b another use for rssi is to determine that transmit power can be reduced in a system. if the rssi detects a strong signal, the transmitter could be alerted to reduce its transmit power and so reduce current consumption. fee the frequency error estimator (fee) counts pulses from inside the demodulator to measure the frequency offset between it?s receive frequency and the transmitter?s frequency. the maximum offset that fee can correctly report a frequency difference is about 20ppm. the output of the fee can be used to tune the xco frequency, both for production calibration and to compensate for crystal temperature drift and aging. the fee is enabled when feec[1:0] = 11, and is off when feec[1:0] = 00 (do not use other values). it has two counters. one counter determines the measurement period by generating a trigger every time it has counted up the number of bit periods selected by the setting of feec[3:2] as given in table 15. a second counter accumulates the net tally of up and dn pulses from the demodulator. for each incoming ?1? bit, up carries an average number of pulses that is twice the modulation index ( ), and likewise for each incoming ?0? bit and dn. the trigger transfers the contents of the second counter to the fee register and clears it, after which it begins accumulating again. feec_1 feec_0 fee mode 0 0 off 0 1 do not use 1 0 do not use 1 1 counting up and dn pulses. up increments the counter, dn decrements it. feec_3 feec_2 no. of bits used for the measurement 0 0 8 0 1 16 1 0 do not use 1 1 do not use table 15. feec (frequency error estimator control) bits the result of the measurement, read from the fee register at address 22 (16 hex, 0010110 binary), is actually an eight-bit two?s complement signed number, which can have values from -128 to 127. reading fee gives the most recently transferred value. the raw fee value, treated as an unsigned number ranging from 0 to 255, can be converted into a signed integer as follows: if fee < 128 then {fee signed = fee} else {fee signed = (fee - 256)}, for a straightforward measurement of frequency offset, the incoming signal has to have an equal number of ones and zeros, such as a 1010? preamble. the frequency offset can then be calculated: signed b offset fee 4p r f = where fee is the value read from the fee register (treated as a signed number), p is the number of data bits over which the count is taken, and r b is the bit rate. when f offset is zero, the transmitter and receiver are perfectly aligned. a positive f offset means that the received signal has a higher frequency than the carrier frequency to which the receiver is tuned. to compensate for this, the receiver?s xco frequency should be increased by reducing xco_tune bits as detailed in t he ?crystal oscillator (xco)? section. counting a larger number of symbols (higher p) improves the accuracy of the measur ement. beware, however, of overflow, which can cause the fee value to jump from +127 to -128 after only one excessive count. if the frequency offset is too large for the chosen p, then p must be reduced. p = 8 or p = 16 is safest.
micrel, inc. MICRF507 march 2010 27 m9999-032210-b xcotune procedure example a procedure such as the algorithm given below can be called during production (storing the calibrated xco_tune value), at regular intervals, or implemented in the communication protocol when the frequency has changed. the MICRF507 measures the frequency offset between the demodulated signal and the lo, and a micro-controller programs the xco_tune bits to tune the xco so the lo frequency is equal to received carrier frequency. procedure description: a transmitter is assumed to be sending a 1010? pattern at the correct frequency and bit rate. the fee is enabled (feec[1:0] = 11) and the number p of bit periods used in the measurement is 8 or 16. only the sign of fee is used. objective: the best xco_t une value (giving the lowest ifeei). the desired frequency of the receiver?s pll is midway between the ?0? and ?1? frequencies. local variables: xco_present: (5-bit) holds current value in xco_tune field xco_step: (4-bit) holds amount by which xco_tune will be incremented or decremented xco_sign: (1 bit) has a value of either pos or neg, determining respectively whether xcotune is to be incremented or decremented (reducing xcotune increases lo frequency) xco_tune_bits is a buffer, which is written to the xcotune field when programrfchip is called. xco tune procedure initialization: xco_present = 16; xco_step = 16; xco_sign = neg; registers properly set for reception; loop: xco_step = xco_step/2; if (xco_sign == pos) then // if pos then increase lo frequency: {xco_present = xco_present - xco_step} else // if neg then decrease lo frequency: {xco_present = xco_present + xco_step} ; xco_tune_bits = xco_present; programrfchip; wait for > p bit periods; read fee; if (fee > 0?) then {xco_sign = pos} else {xco_sign = neg} // negative or 0 ; if (xco_step > 1) then {branch to loop} else {if(xco_sign == pos) then {xco_present = xco_present ? 1; return (xco_present)}; \\ done } ;
micrel, inc. MICRF507 march 2010 28 m9999-032210-b transmitter power amplifier the maximum output power of the power amplifier (pa) is approximately 10dbm with a 50 ? load. for maximum output power, the load seen by the pa must be resistive. higher output power can be obtained by decreasing the load impedance, but this will conflict with impedance matching to the lna. the output power is programmable in seven levels by means of the pa[2:0] field, with approximately 2.5db between steps; see table 17. the power amplifier is turned off when pa[2:0] = 000. otherwise the pa is on and output power increases with the value of the pa[2:0] field and is maximum when pa[2:0] = 111. setting pa_by=1 causes the pa to be bypassed and output power to drop by ~22db. it is still possible to control the power with pa[2:0] bits. the lc filter shown in figure 18 reduces harmonic emission when placed between the ant pin and antenna. field name number of bits location of bits description reference modulation 2 reg1[7:6] modu lation selection table 18 mod_i 5 reg4[4:0] modulator current setting mod_a 4 reg5[3:0] modulator attenuator setting mod_f 3 reg4[7:5] modulator filter setting pa 3 reg0[6:4] power amplifier level table 17 pa_by 1 reg2[4] bypass of pa stage on/off table 17 table 16. register bit fields for transmitter and vco modulation pa2 pa1 pa0 state (approximate attenuation) 0 0 0 pa off 0 0 1 15db attenuation 0 1 0 12.5db attenuation 0 1 1 10db attenuation 1 0 0 7.5db attenuation 1 0 1 5db attenuation 1 1 0 2.5db attenuation 1 1 1 max output pa_by 0 power amplifier enabled 1 power amplifier bypassed, approx 20db reduced output power. table 17. register bit fields for power amplifier
micrel, inc. MICRF507 march 2010 29 m9999-032210-b c4 12pf c5 39pf 12pf c6 l1 12nh ant (pin 5) figure 18. lc filter this filter is designed for the 490mhz band with 50 ? terminations. component values may have to be tuned to compensate for layout parasitics. frequency modulation the MICRF507 supports two methods of fsk modulation, selected with the modulation field as shown in table 18: vco modulation (enabled when modulation1 is bit set to 0) and divider modulation (modulation1 bit set to 1). the modulation0 bit must always remain 0. modulation1 modulation0 state 0 0 closed loop vco-modulation 0 1 not in use 1 0 modulation by a,m and n 1 1 not in use table 18. modulation field bits from the microcontroller to be transmitted enter at the dataixo pin. see table 19. the modulation index ? must be a minimum of 2. it is given by b dev r f 2 = in which f dev is the single-sided deviation and r b is the bit rate. another constraint on f dev is f dev r b + f offset where f offset is the total frequency offset between the receiver and the transmitter: the calculated f dev should be used to calculate the needed receiver bandwidth, see ?switched capacitor filter? section. vco modulation frequency divider modulation set modulation[1:0] to 00 10 means of modulation vco modulation using modulator divider modulation by switching between a0/m0/no and a1/m1/n1 register fields to set refclk_k, mod_clks, mod_i, mod_a, mod_f a0, m0, n0, a1, m1, n1 pll bandwidth required lower than 1/10 of bit rate higher than 2x bit rate bitstream constraints dc balance required none instantaneous frequency waveform (spectrum) determined by register fields affecting modulator pll transient response table 19. modulation modes
micrel, inc. MICRF507 march 2010 30 m9999-032210-b divider modulation when modulation[1:0] = 10, two sets of divider values need to be programmed. the divider values stored in the m0, n0, and a0 registers are selected to transmit a ?0? and the m1, n1, and a1 registers are selected to transmit a ?1?. 2m0 a0 n0 16 f f xco rf0 + = 2m1 a1 n1 16 f f xco rf1 + = the carrier frequency that a receiver must be set to in order to receive the above transmitted signal is: 2 f f f rf1 rf0 rf + = and the single-sided deviation is: 2 f f f rf0 rf1 dev ? = the pll must lock to a new frequency upon every transition in the transmitted bitstream and therefore, needs a high bandwidth, at least twice the bit rate. vco modulation and the modulator vco modulation is selected when modulation[1:0] = 00. the modulator generates a waveform with programmable amplitude and shape. this waveform is fed into a modulation varactor in the vco, which performs the desired frequency modulation. the synthesizer operates with a=a0, m=m0, and n=n0. to create the modulating waveform the modulator charges and discharges a capacitor, controlled by a modulator clock. as shown in figure 19, each transition of the waveform takes four periods of the modulator clock. charge/discharge current, and therefore slope, varies so as to ?round? the waveform and reduce the transmission spectral width. the amplitude of the modulating waveform, and therefore frequency deviation, is determined by the modulation clock frequency (controlled by the crystal oscillator frequency and the register fields refclk_k, and mod_clks), the charge/discharge current (contr olled by the register field mod_i), and the setting of an attenuator (controlled by the register field mod_a). the e ffects of these factors are explained and quantified belo. a filter is provided to optimize transmit bandwidth, the proper setting of which is also explained below. the synthesizer is a negative feedback loop that suppresses perturbations inside the loop (including the modulating varactor control voltage) below its bandwidth. the pll will not allow modulation unless its transient response is slower than the bitstream pulses. frequency deviation is a high-pass response to modulation. this means that when vco modulation is used, the loop bandwidth must be less than the lowest baseband spectral component of the bitstream. it also means that the bitstream must be dc-free (have an equal number of ones and zeros). see ?dc balanced line coding? section. m odulator clock m odulator waveform figure 19. modulator waveform and clock
micrel, inc. MICRF507 march 2010 31 m9999-032210-b frequency deviation under vco modulation three factors determine the deviation at which the data stream is modulated: modulator clock frequency, capacitor charge/discharge current, and modulator attenuator setting. after each is presented in turn, the complete formula for deviation is given. the modulator clock frequency is determined by the crystal oscillator frequency and the settings of the refclk_k and mod_clks fields: mod_clks) - (7 xco mod_clk 2 refclk_k f f = set the modulator clock frequency to either 8x or 16x the frequency deviation rate. figure 20. two different modulator clock settings having f mod_clk set at 8 times the bit rate corresponds to a baseband data signal filtered in a gaussian filter with a bandwidth-period product (bt) of 1. when bt is increased, the waveform will be less filtered. figure 20 shows two waveforms with bt=1 (the minimum, with f mod_clk at 8 times the bitrate) and bt=2 (with f mod_clk at 16 times the bit rate). changing bt changes the charge-and discharge times and therefore the frequency deviation, as seen in figure 20. the capacitor charge/discharge current , set with the mod_i field, affects deviation, as shown in figure 21, where mod_ia>mod_ib. higher current will give a higher frequency deviation and vice versa. the effect of modulator clock and mod_i is as follows: mod_clk dev f mod_i f to avoid saturation in the modulator, it is important not to exceed maximum mod_i. maximum mod_i for a given f mod_clk is given by: 1 - ) 10 28 int(f mod_i -6 mod_clk max ? = where int() returns the integer part of the argument. figure 21. two different modulator current settings a third factor determining deviation is the modulator attenuator , controlled by the mod_a field. the attenuator is used when the bit rate is small and/or the bt is small, which gives a relatively slow modulator clock and therefore long rise- and fall times, leading in turn to large frequency deviations unless the signal is attenuated. additionally, the attenuator will improve the resolution in the modulator. figure 22. two different modulator attenuator settings the effect of the attenuator is given by: mod_a 1 1 f dev +
micrel, inc. MICRF507 march 2010 32 m9999-032210-b figure 22 shows two waveforms with different attenuator setting: mod_ab mod_aa < . if mod_a is increased, the frequency deviation is lowered and vice versa. the resulting frequency deviation in terms of the parameters discussed above is given in the following equations: mod_clks) (7 xco mod_clk 2 refclk_k f f ? = () rf 2 1 mod_clk dev f c c mod_a 1 f mod_i f + + = 1 where: f dev : single sided frequency deviation [hz] f xco : crystal oscillator frequency [hz] f rf : center frequency [hz] refclk_k: 6 bit divider, values between 1 and 63 mod_clks: modulator clock setting, values between 0 and 7 f mod_clk : modulator clock frequency, derived from the crystal frequency, refclk_k and mod_clks mod_i: modulator current setting, values between 0 and 31 mod_a: modulator attenuator setting, values between 0 and 15 c 1 : -2.72 x 10 10 c 2 : 85.2 note that the constants c 1 and c 2 are empirically derived. actual frequency deviation may differ by a few percent. modulator filter to reduce the high-frequency components in the generated waveform, a filter with programmable cut-off frequency can be enabled. this is done using mod_f[2:0], bit 0 being lsb. the mod_f field should be set according to the formula: b 3 r bps 150x10 mod_f = figure 23. modulator waveform with and without filtering in which r b is the bit rate in bits/sec. mod_f=0 disables the modulator filter and mod_f=7 pr ovides the most filtering. figure 23 shows a waveform with and without the filter. the modulator filter will not influence the frequency deviation as long as the programmed cut-off frequency is above the actual bit rate.
micrel, inc. MICRF507 march 2010 33 m9999-032210-b system modes and initialization start-up and in itialization after supply voltage is applied to the MICRF507, a power on reset period elapses during which it should be considered to be in an unknown state. the microcontroller should wait until power on reset is completed. see ?power-on reset? subsection within the ?control (3-wire) interface? section. after power-on is completed, all 22 writeable registers must be correctly initialized before operation of the MICRF507. write only non-zero values to the m0, n0, m1, and n1 fields. modes of operation mode1 mode0 state comments 0 0 power down keeps register configuration 0 1 standby only crystal oscillator running 1 0 receive full receive 1 1 transmit full transmit except pa state table 20. main mode bits mode transitions to go from power down mode to either receive or transmit mode, the MICRF507 needs to go through the standby mode first. this is to ensure that the crystal oscillator starts up correctly. once the crys tal oscillator settles, the MICRF507 can go to receive or transmit mode. when the mode has been changed to transmit or receive, or when the power amplifier has been enabled, the synthesizer must be allowe d to stabilize. see ?lock detect? section. when using vco modulation; after MICRF507 has been put in transmit mode, the micr ocontroller will tri-state the driver connected to dataixo pi n to leave that pin floating until the microcontroller begins sending data. this is because in transmit mode, the modulator is disabled while the dataixo pin is floating (a weak voltage divider sets its level at vdd/2) in order to prevent a performance- degrading transient when message transmission begins. below, ?write to registers? means writing a complete control word, or writing just to registers that need to change. transition to transmit mode: ? write to registers, setting transmit mode, and other changes as needed; set/keep pa off (to reduce spurious emissions). this makes dataixo an input. ? write to registers setting pa on (this requires updating register 0 only). ? wait for ld. ? enable the microcontroller?s pin as an output driving dataixo and begin sending the transmit bitstream. ? after the last bit is transmitted return the microcontroller?s pin to being an input. transition to receive mode: ? have the microcontroll er?s dataixo driver disabled. ? write to registers setting receive mode and other changes as needed. ? wait for ld. or, if desired, commence checking the received bitstream for a valid message without waiting. field name number of bits location of bits description reference mode 2 reg0[2:1] main mode selection table 20 outs 4 reg2[3:0] test pins output table 28 table 21. register bit fields for system functions
micrel, inc. MICRF507 march 2010 34 m9999-032210-b message coding and formatting dc balanced line coding line coding, diagrammed in figure 24, is used when a communication channel imposes constraints on bit sequences. an encoding stage that ensures dc balance (equal numbers of ?1? and ?0? bits and no long consecutive runs of either) in the encoded bit stream allows the use of vco modulation without restri ctions on the message bit stream. of the coding schemes which meet this need, manchester encoding and 3b 4b are among the most commonly used. programming and performance of the MICRF507 are based on the encoded bit rate. in manchester encoding, each message bit maps to a word made of two encoded bits as shown in table 22. the encoded bit rate is twice the message bit rate so the encoding overhead is 100%. when selecting pll loop filter it is important to note that frequency content of the encoded bit stream extends down to one-fourth of the encoded bit rate. that is the case of a 0101? message bit sequence, which results in a 100110011001? encoded bit sequence. data word ?0? ?10? ?1? ?01? table 22. manchester encoding another encoding method, which is much more efficient than manchester coding, is 3b4b, where three message data bits are encoded into a four-line-bit word. the encoded bit rate is three-quarter times the message bit rate. for perfect dc balance, a four bit word would have to have two ?1? line bits and two ?0? line bits. only six such words are possible. special steps are therefore needed to deal with the remaining two encodings: whenever 000 and 111 data appear, toggle a flag that remembers whether the last encoded word was taken from the ?word a? column and select the respective word from the other column shown in table 23. data word a word b 000 1011 0100 001 1100 010 0011 011 1010 100 0101 101 1001 110 0110 111 1101 0010 table 23. 3b4b encoding data bits encoded words comments 000 000 000 000 000 1011 0100 1011 0100 1011 a flag indicates if ?word a? has been used 111 111 010 110 000 1101 0010 0011 0110 1011 a flag indicates if ?word a? has been used table 24. example of 3b4b encoding message formatting: preamble messages are typically preceded by a header consisting of 24 bits in an alternating pattern: 0101? such a header can permit the following actions by the receiver prior to the arrival of information-carrying bits: ? reading of rssi ? bit synchronizer lock-up ? using the fee to null out frequency offset figure 24. link architecture with encoding
micrel, inc. MICRF507 march 2010 35 m9999-032210-b typical application
micrel, inc. MICRF507 march 2010 36 m9999-032210-b bill of materials item part number manufacturer description qty. c1 grm188r71c103k murata (1) 0.01f, 16v capacitor, x7r 10%, size 0603 1 c2 grm219r71c104k murata (1) 0.1f, 16v capacitor, x7r 10%, size 0805 1 c3 no connect 0 c4 grm1885c1h120j murata (1) 12pf, 50v capacitor, cog 5%, size 0603 1 c5 grm1885c1h390j murata (1) 39pf, 50v capacitor, cog 5%, size 0603 1 c6 grm1885c1h120j murata (1) 12pf, 50v capacitor, cog 5%, size 0603 1 c7 grm155r61a102k murata (1) optional 1000pf 1 c8, c9 grm1555c1h1r5c murata (1) 1.5pf, 50v capacitor, cog 0.25pf, szie 0402 2 c10 grm155r61a102k murata (1) 1000pf, 10v capacitor, x5r 10%, size 0402 1 c11 grm155r71h221k murata (1) 220pf, 50v capacitor, x7r 10%, size 0402 1 c12, c13 grm155r61a102k murata (1) 1000pf, 10v capacitor, x5r 10%, size 0402 2 r1 crcw04026200rjk vishay (2) 6.2k resistor, 5%, size 0402 1 r2 crcw04020rjk vishay (2) 0 ? resistor, 5%, size 0402 1 r3 crcw040227kjk vishay (2) 27k resistor, 5%, size 0402 1 r5 crcw040282kjk vishay (2) 82k resistor, 5%, size 0402 1 r6 crcw040233kjk vishay (2) 33k resistor, 5%, size 0402 1 r7 crcw04020rjk vishay (2) 0 ? resister, 5% size 0402 1 l1 0603cs-12nxjb coilcraft (3) 12nh, 5%, size 0603 1 y1 tsx-10a16.0000mhz: tn4-26011 toyocom (4) 16mhz, 9pf, 10/10ppm 1 u1 MICRF507 micrel, inc. (5) 470mhz to 510mhz low-power fsk transceiver with +10dbm power amplifier 1 notes: 1. murata: www.murata.com 2. vishay: www.vishay.com 3. coilcraft: www.coilcraft.com 4. toyocom: www.epsontoyocom.co.jp/english 5. micrel, inc.: www.micrel.com
micrel, inc. MICRF507 march 2010 37 m9999-032210-b layout considerations to ensure the best rf performance, a carefully planned layout is essential. groundi ng, rf path geometry, supply routing, and layer definition all play a role in an optimal design. these are discussed below, and a recommended layout can be found on the micrel website ( www.micrel.com ). layer definition a typical MICRF507 pcb design consists of four layers, with the following stack-up: layer1 ? component and rf routing layer2 ? ground layer3 ? vdd routing layer 4 ? non-rf routing while not the only acceptable definition, this example provides a good foundation for the general techniques discussed below. grounding design the layout to provide the shortest possible return path for signals and noise s ources. place ground vias close to all critical items such as ground pins on the rf ic, decoupling capacitors, and matching components. rf traces the ant pin impedance is approximately 50 ? . to minimize reflection due to impedance mismatch, rf traces should be a controlled impedance of 50 ? as well. refer to the micrel development board layout, or a transmission line impedance calculator to verify a specific geometry?s characteristic impedance. supply routing the radio system is sensitive to supply noise and signals coupled from one section to another. routing the supply lines on an internal layer (below the ground layer) separates them from potential noise sources such as the reference oscillator, pa, char ge pump, etc. route supplies separately and place bypass capacitors as close as possible to the associated pin. pll loop filter place loop filter components close to each other and near pins 27 and 29. connection of the loop filter to vdd should occur very close to vcov dd, pin 31. avoid routing potentially noisy busses or traces near the loop filter.
micrel, inc. MICRF507 march 2010 38 m9999-032210-b overview of programming bits address field data field a6..a0 d7 d6 d5 d4 d3 d2 d1 d0 0000000 lna_by pa2 pa1 pa0 sync_en mode1 mode0 load_en 0000001 modulation1 modulation0 ol_opamp_en (?0?) pa_ldc_en (?0?) rssi_en ld_en pf_fc1 pf_fc0 0000010 cp_hi sc_by vco_by (?0?) pa_by outs3 outs2 outs1 outs0 0000011 ifbias_s (?1?) ifa_hg (?1?) vco_bias_s (?0?) vco_ib2 vco_ib1 vco_ib0 vco_freq 1 vco_freq0 0000100 mod_f2 mod_f1 mod_f0 mod_i 4 mod_i3 mod_i2 mod_i1 mod_i0 0000101 - - mod_fhg (?0?) mod_shape (?1?) mod_a3 mod_a2 mod_a1 mod_a0 0000110 - mod_clks2 mod_clks1 mod_clks0 bitsync_clks2 bitsync_clks1 bitsync_cl ks0 bitrate_clks2 0000111 bitrate_clks1 bitrate_clks0 refclk_k5 re fclk_k4 refclk_k3 refclk _k2 refclk_k1 refclk_k0 0001000 sc_hi (?1?) scclk_x2 (?1?) scsw_en (?0?) scclk4 scclk3 scclk2 scclk1 scclk0 0001001 prescalmode_s (?0?) prescal_s (?0?) xcoar_en (?1?) xcotune4 xcotune3 xcotune2 xcotune1 xcotune0 0001010 - - a0_5 a0_4 a0_3 a0_2 a0_1 a0_0 0001011 - - - - n0_11 n0_10 n0_9 n0_8 0001100 n0_7 n0_6 n0_5 n0_4 n0_3 n0_2 n0_1 n0_0 0001101 - - - - m0_11 m0_10 m0_9 m0_8 0001110 m0_7 m0_6 m0_5 m 0_4 m0_3 m0_2 m0_1 m0_0 0001111 - - a1_5 a1_4 a1_3 a1_2 a1_1 a1_0 0010000 - - - - n1_11 n1_10 n1_9 n1_8 0010001 n1_7 n1_6 n1_5 n1_4 n1_3 n1_2 n1_1 n1_0 0010010 - - - - m1_11 m1_10 m1_9 m1_8 0010011 m1_7 m1_6 m1_5 m 1_4 m1_3 m1_2 m1_1 m1_0 0010100 div2_hi (?1?) lo_ib1 (?0?) lo_ib0 (?1?) pa_ib4 (?1?) pa_ib3 (?0?) pa_ib2 (?1?) pa_ib1 (?0?) pa_ib0 (?1?) 0010101 - - - - feec_3 feec_2 feec_1 feec_0 0010110 fee_7 fee_6 fee_5 fee_4 fee_3 fee_2 fee_1 fee_0 table 25. overview of register bits
micrel, inc. MICRF507 march 2010 39 m9999-032210-b detailed description of programming bits adr # bit # name description comments 0000000 7 by_lna lna bypass on/off 6 pa2 power amplifier level, 3.bit reference table 17 5 pa1 power amplifier level, 2.bit reference table 17 4 pa0 power amplifier level, 1.bit reference table 17 3 sync_en synchronizer mode bit reference table 7 2 mode1 main mode selection 2.bit reference table 20 1 mode0 main mode selection 1.bit reference table 20 0 load_en ?1? mandatory 0000001 7 modulation1 modulation selection 2.bit reference table 18 6 modulation0 modulation selection 1.bit reference table 18 5 ol_opamp_en ?0? mandatory 4 pa_ldc_en ?0? mandatory. pa on/off controlled by lock detect pin if this bit is 1 3 rssi_en rssi function on/off 2 ld_en lock detect function on/off 1 pf_fc1 pre-filter corner frequency 2.bit reference table 14 0 pf_fc0 pre-filter corner frequency 1.bit reference table 14 0000010 7 cp_hi high charge-pump current (4x=500ua) on/off 6 sc_by bypass of switched capacitor filter on/off 5 vco_by ?0? mandatory. bypass of vco stage on/off 4 pa_by bypass of pa stage on/off 3 outs3 test pins output 4.bit reference table 28 2 outs2 test pins output 3.bit reference table 28 1 outs1 test pins output 2.bit reference table 28 0 outs0 test pins output 1.bit reference table 28 0000011 7 ifbias_s ?1? mandatory. 6 ifa_hg ?1? mandatory.high gain setting in preamplifier 5 vco_bias_s ?0? mandatory.select separate bias for vco on vcobias pin 4 vco_ib2 vco bias current setting, 3. bi t (111 = highest current) reference table 11 3 vco_ib1 vco bias current setting, 2. bit (100 = typical current) reference table 11 2 vco_ib0 vco bias current setting, 1. bit reference table 11 1 vco_freq1 frequency setting of vco, 2. bit (11=highest frequency) reference table 11 0 vco_freq0 frequency setting of vco, 1.bit reference table 11 0000100 7 mod_f2 modulator filter setting, msb 6 mod_f1 modulator filter setting 5 mod_f0 modulator filter setting, lsb 4 mod_i4 modulator current setting, msb 3 mod_i3 modulator current setting 2 mod_i2 modulator current setting 1 mod_i1 modulator current setting
micrel, inc. MICRF507 march 2010 40 m9999-032210-b adr # bit # name description comments 0 mod_i0 modulator current setting, lsb 0000101 7 --------- reserved/not in use 6 --------- reserved/not in use 5 mod_fhg ?0? mandatory. modulator test bit. 4 mod_shape ?1? mandatory.modulator shape enable 3 mod_a3 modulator attenuator setting, lsb 2 mod_a2 modulator attenuator setting 1 mod_a1 modulator attenuator setting 0 mod_a0 modulator attenuator setting, msb (=0: attenuator active) 0000110 7 --------- reserved/not in use 6 mod_clks2 modulator clock setting 3.bit 5 mod_clks1 modulator clock setting 2.bit 4 mod_clks0 modulator clock setting 1.bit 3 bitsync_clks2 bitsync clock setting 3.bit 2 bitsync_clks1 bitsync clock setting 2.bit 1 bitsync_clks0 bitsync clock setting 1.bit 0 bitrate_clks2 bitrate clock setting 3.bit 0000111 7 bitrate_clks1 bitrate clock setting 2.bit 6 bitrate_clks0 bitrate clock setting 1.bit 5 refclk_k5 reference clock divider 6.bit 4 refclk_k4 reference clock divider 5.bit 3 refclk_k3 reference clock divider 4.bit 2 refclk_k2 reference clock divider 3.bit 1 refclk_k1 reference clock divider 2.bit 0 refclk_k0 reference clock divider 1.bit 0001000 7 sc_hi ?1? mandatory. switced cap filter high current setting on/off 6 scclk_x2 ?1? mandatory. switced cap clock mulitplied by two 5 scsw_en ?0? mandatory. switch cap switch enable 4 scclk4 switchcap clock divider 5.bit 3 scclk3 switchcap clock divider 4.bit 2 scclk2 switchcap clock divider 3.bit 1 scclk1 switchcap clock divider 2.bit 0 scclk0 switchcap clock divider 1.bit 0001001 7 prescalmode_s ?1? mandatory. select external control of prescal mode (div32/33) 6 prescale_s ?0? mandatory. select external control of prescale mode (div 32/33) 5 xcoar_en ?1? mandatory. xco amplitude regulation on/off 4 xcotune4 crystal oscillator trimming, lsb 3 xcotune3 crystal oscillator trimming 2 xcotune2 crystal oscillator trimming 1 xcotune1 crystal oscillator trimming
micrel, inc. MICRF507 march 2010 41 m9999-032210-b adr # bit # name description comments 0 xcotune0 crystal oscillator trimming, msb 0001010 7 --------- reserved/not in use 6 --------- reserved/not in use 5 a0_5 a0-counter 6.bit 4 a0_4 a0-counter 5.bit 3 a0_3 a0-counter 4.bit 2 a0_2 a0-counter 3.bit 1 a0_1 a0-counter 2.bit 0 a0_0 a0-counter 1.bit 0001011 7 --------- reserved/not in use 6 --------- reserved/not in use 5 --------- reserved/not in use 4 --------- reserved/not in use 3 n0_11 n0-counter 12.bit 2 n0_10 n0-counter 11.bit 1 n0_9 n0-counter 10.bit 0 n0_8 n0-counter 9.bit 0001100 7 n0_7 n0-counter 8.bit 6 n0_6 n0-counter 7.bit 5 n0_5 n0-counter 6.bit 4 n0_4 n0-counter 5.bit 3 n0_3 n0-counter 4.bit 2 n0_2 n0-counter 3.bit 1 n0_1 n0-counter 2.bit 0 n0_0 n0-counter 1.bit 0001101 7 --------- reserved/not in use 6 --------- reserved/not in use 5 --------- reserved/not in use 4 --------- reserved/not in use 3 m0_11 m0-counter 12.bit 2 m0_10 m0-counter 11.bit 1 m0_9 m0-counter 10.bit 0 m0_8 m0-counter 9.bit 0001110 7 m0_7 m0-counter 8.bit 6 m0_6 m0-counter 7.bit 5 m0_5 m0-counter 6.bit 4 m0_4 m0-counter 5.bit 3 m0_3 m0-counter 4.bit 2 m0_2 m0-counter 3.bit 1 m0_1 m0-counter 2.bit 0 m0_0 m0-counter 1.bit 0001111 7 --------- reserved/not in use 6 --------- reserved/not in use
micrel, inc. MICRF507 march 2010 42 m9999-032210-b adr # bit # name description comments 5 a1_5 a1-counter 6.bit 4 a1_4 a1-counter 5.bit 3 a1_3 a1-counter 4.bit 2 a1_2 a1-counter 3.bit 1 a1_1 a1-counter 2.bit 0 a1_0 a1-counter 1.bit 0010000 7 --------- reserved/not in use 6 --------- reserved/not in 7use 5 --------- reserved/not in use 4 --------- reserved/not in use 3 n1_11 n1-counter 12.bit 2 n1_10 n1-counter 11.bit 1 n1_9 n1-counter 10.bit 0 n1_8 n1-counter 9.bit 0010001 7 n1_7 n1-counter 8.bit 6 n1_6 n1-counter 7.bit 5 n1_5 n1-counter 6.bit 4 n1_4 n1-counter 5.bit 3 n1_3 n1-counter 4.bit 2 n1_2 n1-counter 3.bit 1 n1_1 n1-counter 2.bit 0 n1_0 n1-counter 1.bit 0010010 7 --------- reserved/not in use 6 --------- reserved/not in use 5 --------- reserved/not in use 4 --------- reserved/not in use 3 m1_11 m1-counter 12.bit 2 m1_10 m1-counter 11.bit 1 m1_9 m1-counter 10.bit 0 m1_8 m1-counter 9.bit 0010011 7 m1_7 m1-counter 8.bit 6 m1_6 m1-counter 7.bit 5 m1_5 m1-counter 6.bit 4 m1_4 m1-counter 5.bit 3 m1_3 m1-counter 4.bit 2 m1_2 m1-counter 3.bit 1 m1_1 m1-counter 2.bit 0 m1_0 m1-counter 1.bit 0010100 7 div2_hi ?1? mandatory. high bias current setting in div2 circuit on/off 6 lo_ib1 ?0 mandatory. bias current setting of lobuffer, 2. bit (11 = highest current)
micrel, inc. MICRF507 march 2010 43 m9999-032210-b adr # bit # name description comments 5 lo_ib0 ?1? mandatory. bias current setting of lobuffer, 1. bit (01 = typical current) 4 pa_ib4 ?0? mandatory. bias current setting of pa, 2. bit (11 = highest current) 3 pa_ib3 ?0 mandatory. bias current setting of pa, 1. bit (01 = typical current) 2 pa_ib2 ?0? mandatory. bias current setting of pabuffer, 3. bit 1 pa_ib1 ?1?mandatory. bias curre nt setting of pabuffer, 2. bit 0 pa_ib0 ?1? mandatory. bias current setting of pabuffer, 1. bit 0010101 7 --------- reserved/not in use 6 --------- reserved/not in use 5 --------- reserved/not in use 4 --------- reserved/not in use 3 feec_3 fee control bit reference table 15 2 feec_2 fee control bit reference table 15 1 feec_1 fee control bit reference table 15 0 feec_0 fee control bit reference table 15 0010110 7 fee_7 fee value, bit 7, msb 6 fee_6 fee value, bit 6 5 fee_5 fee value, bit 5 4 fee_4 fee value, bit 4 3 fee_3 fee value, bit 3 2 fee_2 fee value, bit 2 1 fee_1 fee value, bit 1 0 fee_0 fee value, bit 0, lsb table 26. detailed description of programming bits
micrel, inc. MICRF507 march 2010 44 m9999-032210-b category field name number of bits location of bits description reference xcotune 5 reg9[4:0] crystal oscillator trimming refclk_k 6 reg7[5:0] reference clock divider bitrate_clks 3 reg6[0], reg7[7:6] bitrate clock setting mod_clks 3 reg6[6:4] modulator clock setting clocking bitsync_clks 3 reg6[3:1] bitsync clock setting datai/f sync_en 1 reg0[3] synchronizer mode bit table 7 m0 12 reg13[3:0], reg14[7:0] m0 counter a0 6 reg10[5:0] a0 counter n0 12 reg11[3:0], reg12[7:0] n0 counter m1 12 reg18[3:0], reg19[7:0] m1 counter a1 6 reg15[5:0] a1 counter n1 12 reg16[3:0], reg17[7:0] n1 counter cp_hi 1 reg2[7] high charge pump current (500 a = 4x) on/off vco_freq 2 reg3[1:0] frequency setting of vco (highest frequency at 11) vco_ib 3 reg3[4:2] vco bias current setting (highest current at 111, 100 typical) synthesizer ld_en 1 reg1[2] lock detect function on/off by_lna 1 reg0[7] lna bypass on/off pf_fc 2 reg1[1:0] pre-filter corner frequency table 14 sc_by 1 reg2[6] bypass of switched capacitor filter on/off scclk 5 reg8[4:0] switched cap clock divider rssi_en 1 reg1[3] rssi function on/off feec 4 reg21[3:0] fee control bits table 15 receive fee 8 reg22[7:0] fee value (read only) modulation 2 reg1[7:6] modulation selection table 18 mod_i 5 reg4[4:0] modulator current setting mod_a 4 reg5[3:0] modulator attenuator setting mod_f 3 reg4[7:5] modulator filter setting pa 3 reg0[6:4] power amplifier level table 17 transmit/vco modulation pa_by 1 reg2[4] bypass of pa stage on/off mode 2 reg0[2:1] main mode selection table 20 system outs 4 reg2[3:0] test pins output table 28 table 27. register fields
micrel, inc. MICRF507 march 2010 45 m9999-032210-b outs3 outs2 outs1 outs0 ichout qchout ichout2 / rssi qchout2 / nc 0 0 0 0 gnd gnd gnd gnd 0 0 0 1 ip mixer in mixer ip ifamp in ifamp 0 0 1 0 qp mixer qn mixer qp ifamp qn ifamp 0 0 1 1 ip ifamp in ifamp ip sc-filter in sc-filter 0 1 0 0 qp ifamp qn ifamp qp sc-filter qn sc-filter 0 1 0 1 ip sc-filter in sc-filter gnd i limiter 0 1 1 0 qp sc-filter qn sc-filter gnd q limiter 0 1 1 1 ip mixer in mixer ip sc-filter in sc-filter 1 0 0 0 qp mixer qn mixer qp sc-filter qn sc-filter 1 0 0 1 ip mixer in mixer gnd i limiter 1 0 1 0 qp mixer qn mixer gnd q limiter 1 0 1 1 ip mixer qp mixer modin prescalmode 1 1 0 0 ip ifamp qp ifamp ti1 tq1 1 1 0 1 ip sc-filter qp sc-filter demodup demoddn 1 1 1 0 i limiter q limiter demod maout 1 1 1 1 n-div m-div phi1n phi2n table 28. test signals
micrel, inc. MICRF507 march 2010 46 m9999-032210-b package information 32-pin mlf ? (ml) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is as sumed by micrel for its use. micrel reserves the right to change ci rcuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems ar e devices or systems that (a) are intend ed for surgical implant into the body or (b) support or sustain life, and whose failure to per form can be reasonably expected to result in a significant inj ury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or system s is a purchaser?s own risk and purchaser a grees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel, incorporated.

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